Short DescriptionAs a techno-manager you will work as part of a team responsible for all phases of product development and are expected to engage with product development teams in India and other Xilinx Development Centers (US)
- B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 10+ years of relevant experience in ASIC/FPGA design.
- Proven end to end design of complex IP using Verilog/System-Verilog/High-Level-Synthesis Languages.
- Strong Micro-Architecture and RTL Design experience.
- Strong domain knowledge of interfaces which include AXI streaming etc
- Strong knowledge of digital electronics and digital systems
- Strong debugging skills
- Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage
- Having System level knowledge / Validating IP at system level and prior working knowledge of the Xilinx implementation tools
- will be a definite plus
- Experience of GPU/DSP design is a plus.
- Understanding of computer-vision and deep-learning algorithms is a huge plus.
- Understanding of hardware/software interface is a plus.
- Self-driven, motivated, result oriented individual with superior academic achievements
- Excellent interpersonal, written, group communication and problem solving skills
- Good organizational and execution skills with ability to multi-task and prioritize
ENGINEERING PROJECT MANAGER 1